One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture

ABSTRACT

There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use &#34;zero power&#34; during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

CROSS-REFERENCES TO RELATED OR COPENDING APPLICATONS

U.S. patent application Ser. No. 07/865,007, filed Apr. 8, 1992,.Iadd.now U.S. Pat. No. 5,235,221, .Iaddend.is a field programmablelogic array with speed optimized architecture, having common assigneewith the present invention.

U.S. patent application Ser. No. 07/817,167, filed Jan. 6, 1992,.Iadd.now U.S. Pat. No. 5,270,587, .Iaddend.is a CMOS logic cell forhigh speed, zero-power programmable array logic devices, having commonassignee with the present application.

U.S. patent application Ser. No. 07/865,007, filed Apr. 8, 1992,.Iadd.now U.S. Pat. No. 5,235,221, .Iaddend.is a field programmablelogic array with speed optimized architecture, having common assigneewith the present invention.

U.S. patent application Ser. No. 07/883,759, filed May 15, 1992,.Iadd.now abandoned, .Iaddend.is a programmable logic device with asingle parameter state decode, having common assignee with the presentinvention.

U.S. patent application Ser. No. 07/884,489, filed May 15, 1992,.Iadd.now U.S. Pat. No. 5,287,017, .Iaddend.is a programmable logicdevice macrocell with two or array inputs, having common assignee withthe present invention.

U.S. patent application Ser. No. .Iadd.07/.Iaddend.883,076, filed May15, 1992, .Iadd.now abandoned, .Iaddend.is a programmable logic devicemacrocell with an exclusive feedback line and an exclusive externalinput line, having common assignee with the present invention.

U.S. patent application Ser. No. 07/884,505, filed May 15, 1992,.Iadd.now abandoned, .Iaddend.is a programmable logic device macrocellwith an exclusive feedback line and an exclusive external input line fora combinatorial mode and accommodating two separate programmable orplanes, having common assignee with the present invention.

U.S. patent application Ser. No. 07/883,843, filed May 15, 1992,.Iadd.now abandoned, .Iaddend.is a programmable logic device macrocellwith an exclusive feedback line and an exclusive external input line fora state counter or registered sum-of-products signal, having commonassignee with the present invention.

U.S. patent application Ser. No. 07/883,078, filed May 15, 1992,.Iadd.now U.S. Pat. No. 5,300,830, .Iaddend.is a programmable logicdevice macrocell with an exclusive feedback line and an exclusiveexternal input line for registered and combinatorial modes using adedicated product term for control, having common assignee with thepresent invention.

U.S. patent application Ser. No. 07/914,361, filed Jul. 15, 1992,.Iadd.now U.S. Pat. No. 5,298,803, .Iaddend.is a field programmablelogic array with a dual or plane macro-cell architecture.

FIELD OF THE INVENTION

The present invention relates to integrated circuits (ICs) architecture.Particularly, there is a Programmable Logic Device, ("PLD") that uses aone time programmable anti-fuse element. Uniquely, a half-latch and fusecell circuit allows the PLD to use "zero power" during the standbyperiod since the sense amps are not used to maintain the programmedlogic. Additionally, the PLD is capable of being tested for logic gateand logic path integrity, and anti-fuse electrical parameters withoutpermanently programming the anti-fuse.

BACKGROUND OF THE INVENTION Historically

The introduction of programmable logic devices (PLD) was a truerevolution in the hardware design world. It enabled engineers to shrinkcircuits requiring several devices onto a single device thus simplifyingtheir designs while saving space and power. Traditionally, PLDs havebeen used in combinatorial circuits such as address decoders as well assequential circuits such as bus arbitration schemes. During the last fewyears, advances and improvements in PLD architectures enabled thedevices to grow more complex while addressing the never-ending quest forhigher density and faster speeds. Despite these improvements, engineersstill face certain problems and limitations with PLDs.

A typical programmable logic device is composed of a user-programmableAND array, a fixed OR gate, followed by an output register whichincludes a feedback path from the output to the programmable AND array.PLDs also have circuitry for programming the inputs to the AND and ORarrays, and for configuring the output macrocells.

Problems

Most PLD architectures have several problems related to the standbycurrent. Standby current is the current required by the chip existingbetween successive inputs to the chip. In other words, its the currentneeded to keep the chip ready for action. Typical PLDs use huge amountsof current during the standby mode, ranging around the hundreds ofmilliamps. This amount of current is an excessive waste when consideringthe limited life of most batteries used in portable computers.

Additionally, other PLDs have gone to the extreme of powering down thechip during standby periods. However, though the chip will not usecurrent during the standby period, it will take typically 15 or morenanoseconds to power up the chip again. This situation creates a hugetiming problem which prevents use in designs requiring 10 ns responsetime.

Another problem is that most PLDs use sense amps in the critical speedpaths during normal operation. This has the effect of using asubstantial amount of power during standby periods. Today's batterypowered computers are severely limited with this type of power usage.

Furthermore, manufactures typically can not test one time programmablePLDs for functionality of the circuits before selling them to customers.In other words, the manufacturer will not be able to know whatpercentage of the IC is inoperative, or know what percentage of thetotal lot sold is defective. This adds extra costs and time delays tocustomers.

Therefore, a need exists for a one time programmable PLD capable of 1)"zero power" during the standby period, 2) testing the fuse electricalparameters, 3) check all of the logic gates for proper functionality,and 4) check all of the logic paths integrity.

It is noted that the above described problems, as well as otherproblems, are solved through the subject invention and will become moreapparent, to one skilled in the art, from the detailed description ofthe subject invention.

SUMMARY OF THE INVENTION

One skilled in the art will appreciate the advantage of the a one timeprogrammable fully-testable programmable logic device with zero powerand anti-fuse cell architecture.

Specifically, one advantage of the invention is to provide "zero power"usage during the standby period. Another advantage is that the fusecapacitances can be tested by the manufacturer before shipping tocustomers without damage to the fuses.

Furthermore, an advantage is that the manufacturer can check all of thelogic gates for proper functionality before selling the one timeprogrammable chips without damaging the fuses.

Additionally, the manufacturer has the advantage of being able to checkall of the logic paths integrity prior to selling the chips withoutdamaging the fuses.

The subject PLD circuit advantageously uses the sense amps strictly forprogram verification operations, and not during normal operationperiods. Thus, providing for a zero power usage during standby periods.

The anti-fuse cells are advantageously used to: 1) program inputs to thearrays, 2) configure the logic of the AND and OR arrays, and 3)configure the macrocell output configurations.

Another advantage of this invention is that there is no need of poweringdown the chip during standby periods.

Other features and objects of the present invention will become moreclear from the following detailed description of the invention, taken inconjunction with the accompanying drawings and claims, or may be learnedby the practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a detailed illustration of the invention.

FIG. 2 is an operation chart for the anti-fuse cell.

FIG. 3 is a timing chart for the invention.

It is noted that the drawings of the invention are not to scale. Thedrawings are merely schematic representations, not intended to portrayspecific parameters of the invention. The drawings are intended todepict only typical embodiments of the invention, and are therefore notto be considered limiting of its scope. The invention will be describedwith additional specificity and detail through the use of theaccompanying drawings.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws "to promote the progressof science and useful arts" (Article 1, Section 8 of the U.S.Constitution).

INCORPORATED MATERIAL

For the purpose of providing background material which may in somerespects illustrate the state of the art, the following books (orarticles or pamphlets) are herein incorporated by reference:"Programmable Logic Handbook," fourth edition, by Monolithic MemoriesInc., 2175 Mission College Blvd.. Santa Clara, Calif., and "PracticalDesign Using Programmable Logic," by D. Pellerin and M. Holley, PrenticeHall, library of Congress no. TK7872 .L64 P44 1991.

The following U.S. patents are herein incorporated by reference forpertinent and supporting information:

U.S. Pat. No. 3,423,646, is a computer logic device consisting of anarray of tunneling diodes, isolators and short circuits.

U.S. Pat. No. 3,566,153, is a programmable sequential logic device.

U.S. Pat. No. 4,124,899, is a programmable array logic circuit.

U.S. Pat. No. 4,499,557, is a programmable cell for use in programmableelectronic arrays.

U.S. Pat. No. 4,569,120, is a method of fabricating a programmable readonly memory cell incorporating an anti-fuse utilizing ion implantation.

U.S. Pat. No. 4,569,121, is a method of fabricating a programmable readonly memory cell incorporating an anti-fuse utilizing deposition ofamorphous semiconductor layer.

U.S. Pat. No. 4,717,912, is an apparatus for producing any one of aplurality of signals at a single output.

U.S. Pat. No. 4,758,746, is a programmable logic array with added arrayof gates and added output routing flexibility.

U.S. Pat. No. 4,763,020, is a programmable logic device having pluralprogrammable function cells.

U.S. Pat. No. 4,796,075, is a fusible link structure for integratedcircuits.

U.S. Pat. No. 4,914,055, is a semiconductor anti-fuse structure andmethod.

U.S. Pat. No. 5,008,855, is a method of programming anti-fuse elements.

U.S. Pat. No. 5,019,532, is a method for forming a fuse and fuse madethereby.

U.S. Pat. No. 5,019,878, is a programmable interconnect or cell usingsilicide MOS transistors.

U.S. Pat. No. 5,068,696, is a programmable interconnect or cell usingsilicide MOS transistors.

U.S. Pat. No. 5,070,384, is an electrically programmable anti-fuseelement incorporating a dielectric and amorphous silicon interlayer.

GENERAL EMBODIMENT

FIG. 1 is a detailed illustration of the invention and includes thefollowing elements: There are two parts to the overall circuit, a halflatch circuit 30, and a fuse cell circuit 29. There is a sense amp 10connected to programmable cells 20 a, b, and c via digit, bit, or columnline 11. There is a power rail Vcc 37. P-channel transistors are 32, 34,and 38, while N-channel transistors are 40, and 42. There is ananti-fuse element 44 coupled between transistor 42 and digit line 11.There are five input signals: 1) power on control (POC*) controllingtransistor 32, test mode ("TM") controlling transistor 38, program("PGM") controlling transistor 40, program anti-fuse ("PGMAF")controlling the programming of anti-fuse 44, and divided Vcc by 2("DVC2") or half Vcc, controlling transistor 42. There is an inverter 36coupled to transistors 38, 40, and 42 as shown. Output 31 is coupled toreceive inputs from inverter 36 and to send the programming informationto the various parts of the IC requiring programming. There is aprogramming circuit 12, which will modify the voltage on the digit line11 to Vpp, or to around 10-15 volts, for permanently programminganti-fuse 44.

OPERATION OF THE INVENTION

One skilled in the art should easily understand the operation of theinvention in reference to FIG. 2 illustrating the timing of theinvention's differing modes.

There is a normal operational mode which is selected to output either azero or one signal to output 31.

There is a power up mode. This is typically the only time POC* isgrounded. This sets all cells to a known Vcc state, and depending uponthe anti-fuse setting, inverter 36 will output either a one or zerosignal.

To program a zero, or pop of the anti-fuse, PGMAF is brought to Vpp orabout 12 volts. This pops the anti-fuse element.

To program a one, or non-pop of the anti-fuse, PGM is brought to ground.Thus, not popping the anti-fuse element.

One skilled in the art will easily understand the verify "0" and "1",and the refresh mode operations in reference to FIG. 2.

Unique to the art is the ability to perform a "dummy" program operation.Specifically, this dummy program allows for testing the IC withoutpermanently programming the anti-fuses. By forcing patterns of ones andzeros in the fuse half latches (32, 34, and 38) with voltages that arenot high enough to pop the fuses, for example around 5 volts testing ofthe entire circuitry can be performed without damage to the one timeprogrammability of the anti-fuses.

To set up for testing of the IC, there is a three step process. First,pulse 1 will reset all fuse latches in the array to a logical one. Next,pulse 2 will load a zero on all the fuse latches in a single row or wordline selected by the PGM signal. Finally, pulse 3 loads a logical one ina selected pattern of fuse latches on the single selected word line, viaPGMAF. Thereby allowing testing of the IC functionality comprising thelogic gates, logic paths, and anti-fuse capacitances.

One skilled in the art will understand that the dummy load inhibit mode,as illustrated, will stop the low test voltages from occurring onselected fuse locations.

To program anti-fuse 44, the PGMAF signal, from program circuit 12 viadigit line 11, is brought up to about Vpp (10-15 volts), while the wordline is simultaneously selected by the PGM signal. Verify mode isinitiated to test the programming of the anti-fuses throughout the IC. Aprogrammed or "one" anti-fuse will force the PGMAF line to "zero" whilean unpopped or "zero" anti-fuse will leave a Vbias level on the PGMAFline.

Power up mode occurs when the IC is first powered up. It is noted thatduring the power up mode that POC* is pulsed low, thus charging node 35to Vcc. If the anti-fuse is set to zero, then inverter 36 will output alow and thereby allow the power rail 37 to charge node 35 throughtransistor 34 instead of 32. If the anti-fuse is set to a one, voltageat node 35 will be pulled low through the anti-fuse and keep theinverter's output high. Once the POC* signal is disabled, theprogramming of the output 31 is set.

Additionally, it is pointed out that DVC2 is either half of Vcc or halfVcc plus one volt most of the time. It is generally know that dielectricanti-fuse cells tend to break down over time because of voltages stressor current leakage. By placing a voltage limiting or protectiontransistor before the anti-fuse, the total amount of stress isdiminished. Thereby, increasing the life of the anti-fuse and inhibitingresistive changes over time.

REMARKS ABOUT THE INVENTION

It is noted that output 31 can be used to control various parts of thePLD. For example, the inputs to the AD and OR arrays, and the macrocellconfigurations can be controlled.

One skilled in the art will also recognize that the sense amps are usedonly for programming verification, and not used during normal operation.Thus, not using any power during standby periods.

Similarly, the use of an anti-fuse provides a means for not using anycurrent in standby periods. If the fuses is not blown, or open, nocurrent flows across it. If blown, there is no current provided fromdigit line 11 during standby mode.

A skilled artisan will notice the use of Vcc/2 power source for the DVC2signal to transistor 42. This is to inhibit the known problems from thetime dependent dielectric breakdown of the anti-fuse. Thus, prolongingthe useful life of the anti-fuse.

Note that operating periods of a PLD are when the PLD is activated andperforming logic-type function of the PLD. Whereas, standby periods arethose times between operating periods when there is no performing oflogic-type functions.

VARIATIONS IN THE INVENTION

There are several obvious variations to the broad invention and thuscome within the scope of the present invention. Uniquely, this inventionmay work with any combination of transistors along the internal circuitpaths. For example, pass gate transistors may be employed for obviousreasons. Similarly, laser fuses or other programmable transistors orcapacitors may be employed over the anti-fuse embodiment. Additionally,although the embodiment is directed to PLDs, the application of theinvention works equally as well for programmable redundancy in DRAMs,and other RAM devices.

While the invention has been taught with specific reference to theseembodiments, someone skilled in the art will recognize that changes canbe made in form and detail without departing from the spirit and thescope of the invention. The described embodiments are to be consideredin all respects only as illustrative and not restrictive. The scope ofthe invention is, therefore, indicated by the appended claims ratherthan by the foregoing description. All changes which come within themeaning and range of equivalency of the claims are to be embraced withintheir scope.

Although subheadings in the Detailed Description of the IllustratedEmbodiment are used, these are merely provided for assisting the reader;wherein, the writer is free to enter any information under anyheading/s.

What is claimed and desired to be secured by United States Patent is:.[.
 1. A programmable logic device, comprising:a sense amp (10); aprogrammable cells (20a) connected to the sense amp, having:a) a halflatch circuit (30), wherein the output (31) from the half latch circuitis used to program various portions of the programmable logic device;and b) a fuse cell circuit (29), coupled to the half latch circuit, forsetting the output of the half latch circuit to a high or low signallevel..]..[.2. The programmable logic device of claim 1, wherein saidhalf latch circuit comprises: a power rail (Vcc 37); and a first (32)and second (34) P-channel transistor, each having the sourceelectrically coupled to the power rail, and the drains coupledtogether..]..[.3. The programmable logic device of claim 2, wherein thehalf latch circuit further comprises:an inverter having electricalinputs from the drains of the first and second P-channel transistors,and having the output electrically coupled to the gate of the secondP-channel transistor, the output of the inverter is the output of thehalf latch circuit for setting a state for various portions of theprogrammable logic device..].4. .[.The programmable logic device ofclaim 3,.]. .Iadd.A programmable logic device, comprising:a sense amp; aprogrammable cell (20a) connected to the sense amp having:a) a halflatch circuit (30), wherein the output (31) from the half latch circuitis used to program various portions of the programmable logic device,.Iaddend.wherein .[.the.]. .Iadd.said .Iaddend.half latch circuit.[.further.]. comprises:a power rail (V_(cc) 37); a first (32) andsecond (34) P-channel transistor, each having the source electricallycoupled to the power rail, and the drains coupled together; an inverterhaving electrical inputs from the drains of the first and secondP-channel transistors, and having the output electrically coupled to thegate of the second P-channel transistor, the output of the inverter isthe output of the half latch circuit for setting a state for variousportions of the programmable logic device; and a third P-channeltransistor (38) having its source electrically coupled to the drains ofthe first and second P-channel transistors.Iadd.; and b) a fuse cellcircuit (29), coupled to the half latch circuit, for setting the outputof the half latch circuit to a high or low signal level.Iaddend..
 5. Theprogrammable logic device of claim 4, wherein said fuse cell circuitcomprises:a first N-channel transistor (42) having the drainelectrically coupled to the source of the third P-channel transistor;and an anti-fuse cell (44) having:a) an input coupled to a digit line(11) which is coupled to the sense amp; and b) an output electricallycoupled to the source of the first N-channel transistor (42).
 6. Theprogrammable logic device of claim 5, further comprising:a secondN-channel transistor (40) having the source coupled to the firstN-channel transistor (42) and the third P-channel transistor (38), andits drain coupled to ground. .[.7. A PLD programming circuit,comprising: an output line (31); fuse circuit means (29), electricallycoupled to the output line, having a low state for pulling the voltageof the first node down, and having a high state for maintaining thevoltage on the first node; and latching circuit means (30), coupled tothe line, having a first mode for outputting a high signal to the outputline while the fuse circuit means is in a low state, and a second modefor outputting a low signal to the output line while the fuse circuitmeans is in a high state..].8. .[.The PLD of claim 7,.]. .Iadd.A PLDprogramming circuit, comprising:a first node (35); an output line (31)connected to the first node of the PLD programming circuit; fuse circuitmeans (29), electrically coupled to the output line, having a low statefor pulling the voltage of the first node down, and having a high statefor maintaining the voltage on the first node, .Iaddend.wherein the fusecircuit means comprises:.[.a.]. .Iadd.the .Iaddend.first node (35),coupled between the fuse circuit and the half latch circuit; a digitline (11); .Iadd.and .Iaddend. an anti-fuse (44), coupled between thedigit line and the first node (35), for enabling the high state on thefirst node when the anti-fuse is unprogrammed, and enabling the lowstate on the first node when the anti-fuse is programmed.Iadd.; andlatching circuit means (30) coupled to the output line of the PLDprogramming circuit, having a first mode for outputting a high signal tothe output line while the fuse circuit means is in a low state, and asecond mode for outputting a low signal to the output line of the PLDprogramming circuit while the fuse circuit means is in a highstate.Iaddend..
 9. The PLD of claim .[.6.]..Iadd.8.Iaddend., furthercomprising:a protection circuit (42), coupled between the first node andthe anti-fuse, for inhibiting the anti-fuse from breaking down overtime.
 10. The PLD of claim 9, further comprising:a program transistor(40) for selectively enabling current through the anti-fuse duringprogramming of the anti-fuse.
 11. The programmable logic device ofclaims .[.1.]..Iadd.4.Iaddend., whereinthe sense amp uses no powerduring operating periods of the programmable logic device.
 12. The PLDprogramming circuit of claim .[.7.]..Iadd.8.Iaddend., furthercomprising:a) a programmable cell including the fuse circuit means andthe latching circuit means; b) a sense amp electrically coupled to theprogrammable cell; and c) the sense amp using no power during operatingperiods of the PLD. .Iadd.13. A semiconductor device having a normaloperating period, said semiconductor device comprising: a sense amprequiring no power during said normal operating period of thesemiconductor device; at least one programmable cell connected to thesense amp, the programmable cell including:a half latch circuit, whereinthe output from the half latch circuit used to program portions of thesemiconductor device wherein the half latch circuit comprises:a powerrail; a first and second P-channel transistors each having the sourcethereof connected to the power rail and the drains thereof connected; aninverter having electrical inputs from the drains of the first andsecond P-channel transistors, and having the output connected to thegate of the second P-channel transistor, the output of the inverter isthe output of the half latch circuit for setting a state for variousportions of the semiconductor device; and a third P-channel transistorhaving its source connected to the drains of the first and secondP-channel transistors; and at least one fuse cell circuit coupled to thehalf latch circuit for setting the output of the half latch circuit to ahigh or low signal level, the fuse cell circuit including:a firsttransistor; and an anti-fuse..Iaddend..Iadd.14. The semiconductor deviceof claim 13, wherein said fuse cell circuit comprises: the firsttransistor comprising a first N-channel transistor having the drainelectrically coupled to the source of the third P-channel transistor;and the antifuse comprising an anti-fuse having:an input connected to adigit line which is coupled to the sense amp; and an output connected tothe source of the first N-channel transistor..Iaddend..Iadd.15. Thesemiconductor device of claim 13, further comprising: a second N-channeltransistor having the source thereof connected to the first N-channeltransistor and the third P-channel transistor having the drain thereofconnected to ground..Iaddend..Iadd.16. A circuit for a semiconductordevice having periods of operation, said circuit comprising:a firstnode; an output line connected to the first node; a fuse circuitconnected to the first node, the fuse circuit having a first state forpulling the voltage of the first node down and having a second state formaintaining the voltage on the first node, the fuse circuit including:adigit line; and an anti-fuse having an unprogrammed state and aprogrammed state, the anti-fuse connected between the digit line and thefirst node enabling the second state on the first node when theanti-fuse is in the unprogrammed state; and a latching circuit connectedto the first node, the latching circuit having a first mode foroutputting a high signal to the output line while the fuse circuit is inthe first state and a second mode for outputting a low signal to theoutput line while the fuse circuit is in the secondstate..Iaddend..Iadd.17. The circuit of claim 16, wherein the fusecircuit comprises: the first node connected between the fuse circuit andthe latching circuit..Iaddend..Iadd.18. The circuit of claim 17, furthercomprising: a protection circuit connected between the first node andthe anti-fuse inhibiting the anti-fuse from breaking down overtime..Iaddend..Iadd.19. The circuit of claim 18, further comprising: aprogram transistor selectively enabling current through the anti-fuseduring programming of the anti-fuse to the programmed state. .Iadd.20.The circuit of claim 14, wherein the first state of the fuse circuitincludes a low state..Iaddend..Iadd.21. The circuit of claim 16, whereinthe second state of the fuse circuit includes a highstate..Iaddend..Iadd.22. The circuit of claim 16, said circuit furthercomprising: the first node being connected between the fuse circuit andhalf latch circuit and connected to the output line; a digit line; andan anti-fuse having a unprogrammed state and programmed state, theanti-fuse connected between the digit line and the first node enablingthe second state of the fuse circuit on the first node when theanti-fuse is unprogrammed and enabling the first state on the first nodewhen the anti-fuse is programmed..Iaddend..Iadd.23. The circuit of claim16, said circuit further comprising:a programmable cell including thefuse circuit and the latching circuit; and a sense amp connected to thefuse circuit using no power during said period of operation of saidsemiconductor device..Iaddend..Iadd.24. A circuit for a semiconductordevice having periods of operation, said circuit comprising: a digitline; a sense amp connected to the digit line, the sense amp using nopower during said operating periods of said semiconductor device; afirst node; an output line connected to the first node; and aprogrammable cell including a fuse circuit connected to the digit lineand the first node and a latching circuit connected to the first nodeand the output line..Iaddend..Iadd.25. The circuit of claim 24, whereinthe programmable cell of said circuit further comprising: the fusecircuit having a first state for pulling the voltage of the first nodedown and having a second state for maintaining the voltage on the firstnode; and the latching circuit having a first mode for outputting a highsignal to the output line while the fuse circuit is in the first stateand a second mode for outputting a low signal to the output line whilethe fuse circuit is in the second state..Iaddend..Iadd.26. The circuitof claim 24, wherein the first state of the fuse circuit includes a lowstate..Iaddend..Iadd. The circuit of claim 24, wherein the second stateof the fuse circuit includes a high state..Iaddend..Iadd.28. The circuitof claim 24, wherein the first state of the fuse circuit includes a lowstate and wherein the second state of the fuse circuit includes a highstate..Iaddend..Iadd.29. The circuit of claim 24, said circuit furthercomprising:the first node being connected between the fuse circuit andlatching circuit and connected to the output line; and the fuse circuitincluding an anti-fuse having an unprogrammed state and programmedstate, the anti-fuse connected between the digit line and the first nodeenabling the second state of the fuse circuit on the first node when theanti-fuse is unprogrammed and enabling the first state on the first nodewhen the anti-fuse is programmed..Iaddend..Iadd.30. The circuit of claim24, wherein the fuse circuit of said circuit further comprising: ananti-fuse having a unprogrammed state and programmed state, theanti-fuse connected between the digit line and the first node enablingthe second state of the fuse circuit on the first node when theanti-fuse is unprogrammed and enabling the first state on the first nodewhen the anti-fuse is programmed..Iaddend..Iadd.31. A circuit for asemiconductor device having periods of operation, said circuitcomprising:an output line; a first node connected to the output line; asense amp using no power during at least one of said operating periodsof said semiconductor device; and a programmable cell including a fusecircuit and latching circuit, the first node connected between the fusecircuit and the latching circuit,wherein the fuse circuit is connectedto the output line, the fuse circuit having a first state for pullingthe voltage of the first node down and having a second state formaintaining the voltage on the first node, the fuse circuit including:adigit line; and an anti-fuse having an un programmed state and aprogrammed state, the anti-fuse connected between the digit line and thefirst node, the unprogrammed state of the anti-fuse enabling the secondstate on the first node and the programmed state of the anti-fuseenabling the first state on the first node when the anti-fuse isprogrammed; and wherein the latching circuit is connected to the outputline, the latching circuit having a first mode for outputting a highsignal to the output line while the fuse circuit is in the first stateand a second mode for outputting a low signal to the output line whilethe fuse circuit is in a second state..Iaddend..Iadd.32. The circuit ofclaim 31, wherein the first state of the fuse circuit includes a lowstate..Iaddend..Iadd.33. The circuit of claim 31, wherein the secondstate of the fuse circuit includes a high state..Iaddend..Iadd.34. Thecircuit of claim 31, wherein the first state of the fuse circuitincludes a low state and wherein the second state of the fuse circuitincludes a high state..Iaddend..Iadd.35. A circuit for a semiconductordevice having periods of operation, at least one of said periods ofoperation being a standby period of operation, said circuitcomprising:an output line; a first node connected to the output line; asense amp using no power during said standby period of operation of saidsemiconductor device; and a programmable cell including a fuse circuitand latching circuit, the first node connected between the fuse circuitand the latching circuit,wherein the fuse circuit is connected to theoutput line, the fuse circuit having a first state for pulling thevoltage of the first node down and having a second state for maintainingthe voltage on the first node, the fuse circuit including:a digit line;and an anti-fuse having an un programmed state and a programmed state,the anti-fuse connected between the digit line and the first node, theunprogrammed state of the anti-fuse enabling the second state on thefirst node and the programmed state of the anti-fuse enabling the firststate on the first node when the anti-fuse is programmed, the programmedstate of the anti-fuse causing no current to be provided from the digitline during said standby period of operation of said semiconductordevice; and wherein the latching circuit is connected to the outputline, the latching circuit having a first mode for outputting a highsignal to the output line while the fuse circuit is in the first stateand a second mode for outputting a low signal to the output line whilethe fuse circuit is in a second state..Iaddend..Iadd.36. The circuit ofclaim 35, wherein the first state of the fuse circuit includes a lowstate..Iaddend..Iadd.37. The circuit of claim 35, wherein the secondstate of the fuse circuit includes a high state..Iaddend..Iadd.38. Thecircuit of claim 35, wherein the first state of the fuse circuitincludes a low state and wherein the second state of the fuse circuitincludes a high state..Iaddend..Iadd.39. A circuit for a semiconductordevice having periods of operation, at least one of said periods ofoperation of said semiconductor device being a standby period, saidcircuit comprising:an output line; a first node connected to the outputline; and a programmable cell including a fuse circuit and latchingcircuit, the first node connected between the fuse circuit and thelatching circuit,wherein the fuse circuit is connected to the outputline, the fuse circuit having a first state for pulling the voltage ofthe first node down and having a second state for maintaining thevoltage on the first node, the fuse circuit including:a digit line; andan anti-fuse having an un programmed state and a programmed state, theanti-fuse connected between the digit line and the first node, theunprogrammed state of the anti-fuse enabling the second state on thefirst node and the programmed state of the anti-fuse enabling the firststate on the first node when the anti-fuse is programmed, the programmedstate of the anti-fuse causing no current to be provided from the digitline during said standby period of operation of said semiconductordevice; and wherein the latching circuit is connected to the outputline, the latching circuit having a first mode for outputting a highsignal to the output line while the fuse circuit is in the first stateand a second mode for outputting a low signal to the output line whilethe fuse circuit is in a second state..Iaddend..Iadd.40. The circuit ofclaim 39, wherein the first state of the fuse circuit includes a lowstate..Iaddend..Iadd.41. The circuit of claim 39, wherein the secondstate of the fuse circuit includes a high state..Iaddend..Iadd.42. Thecircuit of claim 39, wherein the first state of the fuse circuitincludes a low state and wherein the second state of the fuse circuitincludes a high state..Iaddend.